A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS

This paper presents a 4-channel time-interleaved (TI) analog-to-digital converter (ADC), where each channel is comprised of a two-stage pipelined asynchronous successive-approximation (ASAR) sub-ADC. The ADC employs two samplers to alleviate the problem of timing skew on the sub-sampler when distributing the clock to the TI channels. To further increase the speed of the ADC, the reset switch in the capacitive digital-to-analog converter of each sub-ADC is also boot-strapped. The ADC is implemented in a 22-nm CMOS FDSOI technology. With a sampling rate of 1.4 GS/s, measurements show that the ADC achieves an SNDR of 50 dB with a low-frequency input. The SNDR drops by only 1.5 dB at Nyquist. Powered by a 0.8 V supply, the total power consumption of the ADC is 37.5 mW, while the ADC core consumes 19.3 mW.