BDD-Based Self-Test Program Generation for Processor Cores

For processor cores embedded in mission-critical devices, post-deployment self-testing is mandatory for reliability assurance. One promising solution to processor self-testing is software-based self-test (SBST). The idea is for the processor under test to execute self-test programs that are tailored to activate faults and observe test responses. This paper proposes a hybrid approach that utilizes justification techniques and test program templates to convert ATPG patterns to self-test programs. First, we develop a BDD-based justification engine which enables test program optimization for fault detection. To reduce the justification complexity, a test program template is used to control and observe general purpose registers; to address the difficulty of BDD construction, circuit partitioning based heuristics are developed. Furthermore, we design a customized test program template for the register file circuit to reduce the test program generation time and improve fault coverage. The proposed techniques are validated on a RISC-V processor and achieve 90.4% transition delay fault coverage-a 4% improvement over our previous template-based approach.