Design and experimental demonstration of high-voltage lateral nMOSFETs and high-temperature CMOS ICs*

This paper reports the design and experimental demonstration of the HV Lateral nMOSFETs along with Low-Voltage CMOS ICs for the advancement of Power IC technology in 4H-SiC. The HV nMOSFETs discussed in this study are designed for operation within the 400-600V range exhibiting the best-in-class trade-off performance in terms of breakdown voltage - specific on-resistance (BV-Ron,sp). The process technology employed in this work was developed with an objective to monolithically integrate the LV CMOS control circuity with the HV nMOSFET. This work wraps around reporting the design and module process developments accompanied by on-wafer characterizations of the HV nMOSFETs and CMOS respectively. Several P-Well and N-Wells were designed for NMOS and PMOS to target the current and voltage requirements. Attempts have been dedicated to accomplishing lower n-type and p-type contact resistances with diverse ohmic stacks along with well-established Ni as the primary ohmic metal. Finally, to validate the potential of the demonstrated CMOS designs, digital CMOS ICs have been demonstrated and characterized under harsh thermal conditions of up to 450 degrees C.