Comprehensive modeling and formulation of split DC link capacitors balancing problem in Three-Phase Three-Level bidirectional AC/DC converters operating with arbitrary power factor

Three-phase three-level AC/DC and DC/AC converters have demonstrated several advantages over their classical two-level counterparts such as better efficiency, enhanced total harmonic distortion, lower dv/dt and lesser overall chip area. T-type and neutral point clamped (NPC) topologies dominate the family of three-phase three level converters, widely used in 10kVA - 100kVA power range. However, control of three-level converters is more complicated than of their classical two-level counterparts due to necessity of adopting an additional voltage loop, aimed to balance partial split DC link voltages. Moreover, the latter contain multiples of triple-base frequency harmonic ripple even under balanced AC-side operation (this does not happen in two-level converters), which should be minimized by the balancing loop mentioned above. The nature of partial DC link ripple formation was analyzed in-depth for unity power factor operation, yet hardly extended to non-unity power factor cases. Moreover, inaccurate conclusions were drawn in some of the related studies. Consequently, this paper focuses on comprehensive modeling and formulation of split DC link capacitors balancing problem in three-phase three-level bidirectional AC/DC converters operating with arbitrary power factor. Analytical expression for dynamics of partial DC link voltages difference is derived and studied in depth. The relation between zero sequence component of modulation signals and neutral point current, tending to unbalance partial DC link voltages is explicitly established for arbitrary power factor values. Practical cases of restricted and unrestricted zero-sequence component of modulation signals are presented. Analytical predictions are shown to be fully supported by simulations based on both switching-cycle-averaged and full switched converter models. Experimental results obtained employing a 10kVA T-type converter prototype operating with restricted zero-sequence component of modulation signals under different power factor values are also given to further validate the presented methodology.