A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift

This brief presents a 10 Gb/s receiver for an application processor (AP)-to-timing controller-embedded display (TED) interface that is capable of recovering its operating frequency fast from the sleep mode under the supply voltage drift. A hybrid clock and data recovery (CDR) loop is employed to support the fast entering and exiting of the sleep mode by adding AND gates to the digital loop filter, while offering good jitter performance by utilizing an analog loop filter. Also supply voltage drift cancellation (SVDC) circuit is added to maintain constant current in the presence of supply voltage drift. Thanks to the hybrid CDR and SVDC, even if the supply voltage drift occurs during the sleep mode, the same frequency is recovered fast without frequency re-tracking. A prototype chip fabricated in 28-nm CMOS technology occupies an active area of 0.089mm2 with 0.99-pJ/bit energy efficiency in the active mode. The measured results show that the frequency is recovered within 36 ns even if the worst-case supply voltage drift occurs during the sleep mode.