Analysis of Airgaps for OFF-State Capacitance Reduction in SOI-CMOS RF Switches

This article analyses the introduction of airgaps in the interconnect network of silicon-on-insulator (SOI)-CMOS-based RF switches to significantly reduce the OFF-state capacitance ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ without degrading the ON-state resistance ${R}_{ \mathrm{\scriptscriptstyle ON}}$ . Based on the 130-nm node of an existing RF-SOI-CMOS technology, an accurate ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ evaluation is performed by calculating the respective contributions of interconnects and the intrinsic transistor separately. The impact of the relative airgap volume is simulated and results in an ultimate ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ reduction of 24.6% when the intermetal dielectric is completely replaced by air. It is shown that most of the reduction in ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ is achieved by introducing airgap at the first metal level. The airgap approach is verified experimentally by partially eliminating the interconnect dielectric of RF switches in postprocess etching steps. A measured ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ improvement of 21.7 (7.2%) and 18.3 fF/mm (6.3%) is demonstrated for 0.14- and 0.16- $\mu \text{m}$ gate length transistors, for which the airgap volume is only partial.