Fatigue behaviour analysis of thermal cyclic loading for through-silicon via structures based on backstress stored energy density

Through-silicon via (TSV) structures are widely used in microelectronic due to the ease of chip interconnection. Few research has focused on investigating the fatigue properties of TSV structures using crystal plasticity finite element (CPFE) simulations. As the process of TSV structures approaches the micron scale, the effects of anisotropic microstructure and grain size on their fatigue behaviours will become necessary. The present work aims to use CPFE simulations to investigate the fatigue properties of TSVs at the microscale. Finite element models with realistic EBSD morphology and orientation are established for four TSV structures with different grain sizes, and CPFE simulations with thermal cyclic loading from -55 degrees C to 125 degrees C are performed. From the energy point of view, the stored energy density based on backstress and strain gradient is proposed as a fatigue indicator parameter (FIP). CPFE simulation results show that low-angle grain boundaries (LAGBs) and high-angle grain boundaries (HAGBs) dominate crack initiation at the top, bottom or edges of the TSV structure, which is still mainly due to the thermal mismatch effect caused by the difference in the coefficients of thermal expansion of the materials. The crack initiation in the internal structure is mainly caused by symmetric grains containing twin boundaries (TBs), or trigrain boundaries, and this is different from the macroscopic simulations. Combined with the local FIPs concentration distribution, the backstress stored energy density is able to capture more details than the cumulative plastic strain because of its direct correlation with the strain gradient, and validates its effectiveness as a FIP.