A 62.5MHz Bandwidth Third-Order VCO-based Sigma-Delta ADC with a Hybrid Architecture.

A sigma-delta analog-to-digital converter (SDADC) based on voltage-controlled oscillator (VCO) with a hybrid architecture is presented, featuring high sampling rate and wide bandwidth (BW). The loop filter is implemented as a hybrid of feed-forward and feed-back structures. As the VCO quantizer (VCOQ) providing an additional first-order noise shaping, the third-order architecture can achieve fourth-order noise shaping. The nonideal effects are analyzed and modeled both independently and collectively, such as amplifier finite gain-bandwidth, nonlinear VCO and other error sources found in the actual circuit. Simulation results show that nonlinear VCO and DAC element mismatch limit SNDR less than 65dB. Benefiting from the hybrid architecture and data-weighted averaging (DWA) technique, the proposed VCO-based SDADC (VCO-SDADC) achieves 76.0 dB signal-to-noise-and-distortion ration (SNDR) for a 5MHz -1.9dBFS input signal in 62.5MHz bandwidth.