Multi-Mode AI Accelerator Architecture for Thermal-Aware 3D Stacked Deep Neural Network Design.

Deep Neural Networks (DNN) find its prominent presence in the AI world. The properties of its algorithms are very well exploited to make its computations power faster and more efficient. One such adaptation requires reduction in the bit width of the operations for DNN. This paper deals about a DNN architecture design with reconfigurable bitwidth accelerator without affecting the accuracy. This proposed architecture is a modified version of Bit Fusion architecture dealing with dynamic bit-level decomposition for accelerating complex DNN computations. The design make computations with less power consumption, and it is more suitable for the trade-offs among the latency, power, and temperature. The micro architecture design of the modified BitFusion using RTL simulations is carried out to evaluate the functionality.