SiGe Qubit Biasing with a Cryogenic CMOS DAC at mK Temperature
ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)(2023)
Abstract
For running advanced algorithms on a universal quantum computer, millions of qubits are required. To make use of quantum effects, state-of-the-art solid-state qubit devices have to be cooled to mK temperatures, which limits the systems’ scalability with room temperature (RT) electronics. We present the direct co-integration of a scalable, fully integrated, eight channel Bias-DAC designed in a 65-nm bulk CMOS technology and a Si/SiGe spin qubit device at the mixing chamber (MC) of a dilution refrigerator operating below 45 mK MC temperature. As a full proof of principle, the bias of a single electron transistor used as a sensing dot, as well as a single and double quantum dot bias of the qubit device is reported. The slow drift of the DAC S& H output circuit of 0.96 $\mu$V/s leads to a calculated prospective power consumption of 64.5 pW/ch for DC qubit bias voltages generated at low temperature.
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Key words
CMOS,cryogenic temperature,quantum computing,spin qubit,cryogenic CMOS,DAC
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