A Suite of Division Algorithms for Posit Arithmetic

Posit ™ arithmetic is a promising alternative to IEEE 754 floating-point arithmetic due to its higher accuracy, larger dynamic range, and bitwise compatibility. While posit arithmetic has been well studied for basic arithmetic operations, division has received little attention. This paper proposes multiple divider designs for posit arithmetic based on digit recurrence and iterative approximation, and evaluates their performance. ASIC synthesis results show that the proposed designs significantly reduce hardware requirements for 32-bit division units compared to previous works by 1.14 × in area, 1.11× in power, and 1.04×in datapath delay. Moreover, the paper introduces an approximate logarithmic posit division that achieves an 8.8×reduction in area and 29×reduction in energy consumption with negligible degradation of the final results, making it suitable for error-tolerant applications.