MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited V DD scaling with optimal V DD (T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.