Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V

The coupling of synchronous digital design techniques with electronic design automation tools and support systems ensured several decades of steadfast evolution of electronics based on semiconductor devices, where humankind now depends on products derived from this evolution. As technology nodes advance towards semiconductor physical limits, the obtainment of better circuits faces challenges such as increased variability. Addressing this and other challenges requires new and/or alternative devices and/or tools, and/or design techniques. Asynchronous quasi-delay insensitive design potentially ensures automatic or streamlined adaptability to several variations plaguing digital design. The Pulsar environment proposes using commercial design automation tools and specific software to enable the high-level design of complex circuits and their automated semi-custom implementation. Several small to medium circuits such as multiply and accumulate pipelined operators, first-in-first-out modules and others helped develop and validate Pulsar's basic functionality. The main contribution of this paper is to demonstrate the feasibility of using an evolved version of Pulsar to design and automatically implement more complex asynchronous quasi-delay insensitive circuits, such as processors, starting from RTL-like descriptions. Results include 174 post-synthesis/post-layout RISC-V processor simulations, originating from 29 synthesis processes, for cycle-times varying from 10ns to 3ns, in 0.25ns steps.