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Cascode GaN HEMT Gate Driving Analysis

Vanessa Heumesser,Jih-Sheng Lai,Hsin-Che Hsieh,Johnny Hsu,Chih-Yi Yang,Edward Y. Chang,Ching-Yao Liu,Wei-Hua Chieng, Yueh-Tsung Hsieh

2023 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)（2023）

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Abstract
The aim of this paper is to analyze the conventional cascode gate driving to understand the switching transition and to provide a design guide for the GaN HEMT and its associated packaging. A double-pulse tester has been designed and fabricated with minimum parasitic inductance to avoid unnecessary parasitic ringing. The switching behaviors in both turn-on and -off are analyzed through topological study and explained through SPICE simulation. Two different cascode devices were tested to show the impact of threshold voltage and low-voltage Si MOSFET selection.
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