A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process

This brief introduces a 1-kb SRAM design that operates at low power utilizing asymmetrical Schmitt-trigger based SRAM cells. By adopting an asymmetrical design, the SRAM cell performance in terms of hold, access, and write capabilities were enhanced. A power reduction and speed compensation circuit is presented in the design. The SRAM is implemented and fabricated on-silicon using a typical 40-nm TSMC CMOS technology. Measurements show that the design can operate up to 210 MHz clock frequency with a 4.23 fJ energy per bit for a supply voltage of 0.8 V. It also has an average delay of 5.659 ns, which is reduced to an average of 1.708 ns when the speed compensation circuit is enabled.