A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

Network-on-chip (NoC) has played a vital role in enabling high-speed and energy-efficient data communication among different cores in a multi- or many-core System-on-Chip (SoC). To mitigate the pessimistic timing margin reversed for severe process, voltage, and temperature (PVT) variations, we presented a wide supply voltage range router with a novel error detection and correction (EDAC) technique adopted in its latch-based pipeline for high energy efficiency. Especially, a unified clock-gated error correction scheme is presented to address dynamic timing errors under PVT variations and functional pipeline stalls when occurring allocation failure (packet fails to obtain an output port) or flow control (the next router stalls the current packet transmitting) in one cycle. Moreover, a latch-based pipeline structure with three non-overlapped clocks is adopted to further reduce the short-path padding overhead, which is significantly increased in the ultra-low voltage (ULV) regime. Consequently, we prototyped a $2\times2\,\,2\text{D}$ mesh NoC test chip with 28-nm CMOS technology. Compared with the margined baseline with a 10% VDD drop, measurement results show that the proposed router enables $1.4\times $ , 32.4%, and 7.5% improvements in frequency, energy, and area, respectively. Furthermore, the proposed techniques can reduce packet loss by $200\times $ and increase throughput by 19.9% for the NoC at 0.4 V, 25 °C.