LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores

The rapid evolution of machine learning applications along with the exponential growth in the Internet of Things (IoT) has driven a surge in demand for high-performance and energy-efficient hardware solutions for Edge AI applications. While traditional Edge AI hardware either falls short in performance or incurs massive power/area overhead, this paper presents a novel RISC-V processor core architecture with instruction set architecture (ISA) extensions that achieves up to 37x performance improvement for a General Matrix Multiply (GEMM) kernel compared to a baseline RISC-V core. Furthermore, this paper proposes an end-to-end framework named LiteAIR5 that encompasses system-level modeling of ISA-extended RISC-V cores, System-on-Chip Generation, Compiler Support, and FPGA emulation. This all-encompassing framework provides users with the ability to develop optimized AI hardware while also taking into account the effects on the entire system.