An Efficient Hardware Design for Fast Implementation of HQC

Hamming Quasi-Cyclic (HQC), as a code-based Key Encapsulation Mechanism (KEM) algorithm, has been selected as one of the three code-based candidates in the fourth round of standardizing post-quantum cryptographic primitives. Efforts are needed for the efficient hardware implementation for HQC. However, in existing hardware designs for HQC, they cost too many clock cycles in the polynomial multiplication module and do not pay enough attention to the decoders used in the decryption. Therefore, this paper presents an improved hardware design for HQC. Through applying a low-latency polynomial multiplication design, every stage of our design saves amounts of clock cycles. Moreover, an efficient Reed-Solomon (RS) decoder based on the enhanced Parallel Inversionless Berlekamp-Massey (ePIBM) algorithm and a Reed-Muller (RM) decoder based on the Fast Hadamard Transform (FHT) algorithm are introduced to reduce the overhead in the decryption. A complete architecture is finally implemented on the Xilinx Artix 7 FPGA (xc7a200t-3). Experimental results show that the proposed design for the HQC-128 requires 25% less area-delay product (ADP) than the latest one in decryption. Furthermore, the proposed design can perform key generation in 0.11ms, encapsulation in 0.22ms, and decapsulation in 0.38ms, which significantly outperforms the state-of-the-art design.