Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits

The efficiency of known algorithms for solving NP- hard problems is constrained by the limitations of conventional von Neumann architectures. Recurrent networks of stochastic neurons are an appealing alternative to conventional computing architectures, as they potentially allow exploring the binary search space of NP-hard problems with limited resources and overheads. In this study, we consider the case of Boolean Satisfiability on small logic functions, with technological implementations based on Spin-Orbit Torque Magnetic Tunnel Junctions. We propose innovative circuit-level implementations of invertible logic architectures for an AND gate and a Full Adder, emphasizing the design constraints of such invertible logic operations. Simulation results demonstrate the feasibility of SOT-based implementations, and their robustness against process variations. The realistic implementation enables identifying the main power efficiency trade-offs.