Towards xBGAS on CHERI: Supporting a Secure Global Memory.

Modern computing systems embrace heterogeneous system architectures to meet high-performance computing requirements. As a result, the Extended Base Global Address Space (xBGAS) project introduced an extension to the RISCV instruction set architecture (ISA) to provide extended addressing capabilities. Although the xBGAS project is currently implemented on the RISC-V ISA, the project's central vision is to include a broad domain of ideas that is not dependent on any single microarchitecture. Therefore, demonstrating the existing xBGAS benchmarks on the ARM ISA would enable working on a real system prototype. The ARM Morello platform is intended as an industrial demonstrator of a capability architecture using Capability Hardware Enhanced RISC Instructions (CHERI). Consequently, understanding the CHERI semantics and identifying the desired features for xBGAS are crucial for making xBGAS portable across platforms. In this work, we investigate creating a software-based xBGAS solution for the Morello platform by porting the xBGAS runtime onto the ARM ISA. First, we revisit the basics of the xBGAS project and the CHERI project to learn what the security benefits of CHERI on xBGAS are by taking advantage of CHERI capabilities. Then, we explore the implementation of the CHERI capabilities and Morello simulators to discuss an adaptation of the scalable xBGAS runtime library to support other ISAs such as ARM.