Multi-dimensional reconciliation encoder with quasi-cyclic LDPC codes on FPGA

Information reconciliation (IR) is an integral part of classical data post-processing in quantum key distribution (QKD) and often constitutes a performance bottleneck. Due to the low signal-to-noise ratio, continuous-variable QKD systems require a IR scheme, such as multi-dimensional reconciliation (MDR), which is particularly computationally intensive.In this work we present the hardware architecture of an MDR encoder employing Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes. We estimate the required number of flip-flops and the latency of its FPGA implementation. Finally, we investigate the computational bottlenecks and identify solutions to improve the scalability of the proposed implementation.