Up to 100-fold Improvement of Threshold Voltage Stability in ITO Transistors.

Amorphous oxide semiconductors (AOS) are promising for back-end-of-line memory and logic field-effect transistors (FETs) due to their low-temperature large-scale deposition, along with high on-state and low off-state currents [1], [2]. However, improving the reliability of AOS transistors is complicated because of their poorly understood threshold voltage ( $V_{\mathrm{T}}$ ) instability under gate bias stress. Recently, researchers have examined the reliability of some AOS FETs [1], [3]–[10], but a comprehensive study to improve $V_{\mathrm{T}}$ stability of indium tin oxide (ITO) FETs is still missing. Here, we compare the $V_{\mathrm{T}}$ shift of ITO FETs under positive bias stress (PBS) for two channel compositions (varied O 2 content) and two contacts (Ni and Pd), investigating uncapped, Hf02 capped, and annealed devices. We achieve up to 100× improvement after capping and annealing, and demonstrate the lowest $V_{\mathrm{T}}$ shift ∼3 mV/(MV/cm) for ITO FETs to date, ∼23× better than previous reports [4].