Formal Analysis of Camouflaged Reconfigurable Circuits

Reconfigurable field effect transistors are an emerging device technology. Reconfigurability between P- and N-type polarity and multiple (control) gates per device make them well suited for static and dynamic layout camouflaging as well as logic locking, watermarking and similar IP protection techniques. In contrast to classical transistors, the devices can provide fully symmetrical I-V characteristics between P- and N-type polarity with equal device geometry. In this paper, we explore logic gate variants and analyze their delay invariance using a fully automated design space exploration backed by probabilistic model checking. We evaluate how this invariance carries over to more complex combinational circuits and latches. Our analysis shows that effective camouflaging using reconfigurable logic gates is indeed achievable and identifies the most promising designs.