Low-Power Single-Slope ADC with a Replica Comparator for Always-on CIS Applications

This paper presents a low-power single-slope analog-to-digital converter (SS-ADC) for always-on complementary metal-oxide-semiconductor (CMOS) image sensor applications. The proposed design features a pixel-signal-prediction-based comparator comprising a main comparator and a replica comparator. The comparator generates a prediction signal based on the difference of auto-zeroed voltage derived from static current differences of two comparators, finally resulting in the reduction of the number of counter toggles. In addition, for further reduction of power consumption, the second-stage amplifier in the main comparator utilizes the proposed positive-feedback bias-sampling technique to cut off the current path after the comparison. The proposed 11-bit SS-ADC is implemented using a 110-nm CMOS process, has a resolution of $640 \times 480$, and operates at a frame rate of 299 frames per second. Simulation results demonstrate that the reduction of the power consumption of SS-ADC with the proposed comparator is about 65%. In addition, we obtained the total power consumption per column of 13.1 $\mu$W and a figure of merit of 44.6 fJ/conv.-step.