An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2023)

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Abstract
This article presents the design of an area/ power-efficient discrete-time (DT) delta-sigma ( $\Delta \Sigma $ ) modulator suitable for multichannel sensor applications. First, the area efficiency of the modulator is achieved by optimizing the size of the sampling capacitor with the compact integrators based on the dynamic-boost inverter (DBI). The DBI is designed to have a small active area of only 0.00044 mm2, due to its self-bias scheme that eliminates the need for additional hardware for biasing circuitry. Second, the power efficiency is improved through the quantitative design approach to reduce the power consumption of the integrators by optimizing the gain–bandwidth product (GBW) of the DBI-based OTA in each integrator. In addition, the static current consumption of the integrators is further reduced due to the power-saving feature of the DBI utilizing the principle of a composite transistor. Finally, the self-bias scheme ensures that the DBI maintains a dc gain of 44.3 dB despite circuit mismatch by balancing the currents of the nMOS and pMOS transistors in the DBI. The prototype modulator, fabricated using 0.18- $\mu \text{m}$ CMOS technology, occupies an active area of 0.0939 mm2. For a 25-kHz bandwidth (BW), the modulator achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 84.0 dB, a peak SNR of 85.1 dB, and a DR of 87.1 dB with a power supply rejection ratio (PSRR) of 56.8 dB and a common-mode rejection ratio (CMRR) of 66.1 dB at a 1.8-V supply. The modulator also maintains an SNDR higher than 82.5 dB and a DR higher than 85.5 dB for a 5–25-kHz BW with an ${\mathrm {FoM}}_{W}$ of 78.4–103.4 fJ/conversion at a 1.5–1.8-V supply.
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Key words
Analog-to-digital converter (ADC),delta-sigma (ΔΣ) modulator,discrete time (DT),inverter,sensor applications
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