Is there a limit when the access resistance impact on the extraction of key GAA NS FETs devices parameters can (not) be avoided?

DC measurements are performed on n-type Si-channel gate-all-around (GAA) vertically stacked lateral nanosheet (NS) FETs. In this work, the impact of varying external access resistance values on extracted device parameters is analysed. Even if the parameters extraction is made using more access resistance insensitive methodologies, such as Y function-based methods, this work shows that in some cases a higher access resistance can still have an impact on the estimated parameter values, in particular for low field mobility. Moreover, by adding an external resistance only on the source side, the impact of this constructed asymmetry is evidenced on the drain current and transconductance characteristics even at low applied drain bias. The impact of the asymmetry may be enhanced by increasing the applied drain bias. A novel and intuitive Y-function strategy is used to estimate the main device electrical parameters.