High Response Decoding System of Resolver Considering Signal Errors

Resolvers are commonly utilized as position sensors to gather angular data. The accuracy of resolver-to-digital conversion (RDC) may be hampered by response times and systematic errors in the demodulation and decoding of resolvers, though. A demodulation technique based on a multistage notch filter is proposed for the phase delay caused by employing a low-pass filter (LPF) in the signal demodulation process. This demodulation algorithm can enhance the decoding system’s response capacity while also removing the specified harmonics. An improved double second-order generalized integrator with frequency-locked loop (IDSOGI-FLL) is developed to extract the positive sequence components of the sine and cosine signals of the resolver in order to address the systematic faults present in the resolver. In comparison to traditional DSOGI-FLL, IDSOGI-FLL has the same amplitude and phase error suppression capabilities as DSOGI-FLL, but it makes up for the dc offset error suppression capability that is lacking in DSOGI-FLL. The effectiveness of the strategy is demonstrated by the experimental results.