Impact of Applied Voltage on Threshold Voltage Instability in Active Load Thin-Film a-IGZO Inverters

This work presents an analysis and modeling of the electrical stress effects caused by different voltages on a logic inverter device circuit based on thin-film transistor (TFT) technology. The study includes the characterization of single indium-gallium-zinc oxide (IGZO) TFTs and inverters with an active load configuration to investigate the behavior of their threshold voltage (V-TH) under various bias voltages. Additionally, an analytical model is used to quantify the impact of electrical stress on the trapping parameters of the dielectric-semiconductor interface. The model demonstrates that the charged trapped concentration increases exponentially with the applied voltage bias, resulting in a significant initial shift in V-TH. Importantly, this analytical model allows the assessment of the electrical stress effect on TFT-based circuits. The findings can inform the determination of a maximum applied voltage bias based on the desired threshold voltage. Furthermore, the model facilitates the estimation of circuit reliability and lifetime by considering the polarization time under different bias conditions.