An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory
2023 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI-TSA/VLSI-DAT(2023)
Abstract
In this paper, an ALL resistive neuromorphic computing (ARNC) platform was demonstrated with Restive-gate FinFET memory, which includes three major building blocks: weight, ReLU, and ADC. The weight consists of 4-bit-per-cell RG-FinFET memory arrays with gradual and symmetrical tuning capability of the conductance, reliable endurance up to 10(5) cycles for whole 16 states, and excellent data retention. ReLU shows linear output responses when the input is positive and sharply cut-off for negative input. The ADC was implemented by a 16 parallel RG-FinFETs, featuring 267 MHz of the operation frequency, 0.28 mu W of the power at V-ec=0.8V, and very small area size of 10(-5) mm(2). It is well-suited for the energy-efficient AI-Inference in CIM.
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Key words
16 parallel RG-FinFETs,4-bit-per-cell RG-FinFET memory arrays,ADC,ALL resistive neuromorphic computing platform,area size,building blocks,energy-efficient AI-Inference,excellent data retention,frequency 267.0 MHz,gradual tuning capability,ReLU,Restive-gate FinFET memory,symmetrical tuning capability,voltage 0.8 V
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