Channel Material Benchmarking of Si and Ge n-and pMOSFETs Considering Effects of Strain and Operating Temperature

Comprehensive benchmarking analyses of Si and Ge n-and pMOSFETs are performed at a relevant technology node (gate length 13 nm) considering effects of strain and temperature (T) using a hybrid approach of atomistic quantum ballistic transport and full-band Monte Carlo (MC) simulation. Current-voltage characteris-tics and performance metrics such as the effective inverter drive current (I-eff) and maximum supply voltage (V-DD,V-max) are explored. For nMOS, Ge may provide significant Ieff improvements especially when strained (uniaxial tensile stress). For pMOS, the Ieff improvement in relaxed Ge pMOS may be limited due to the large tunneling leakage [direct source-to-drain tunneling (SDT), band-to-band tun-neling (BTBT)], and the improvement by strained Ge pMOS (uniaxial compressive stress) may be also limited by the increased SDT. As T rises above the room temperature (RT), however, Ge n-and pMOS may offer additional perfor-mance benefits. The VDD,max of Ge n-and pMOS increases at high T because tunneling leakage does not increase as much with T. In addition, for devices that have large SDT such as the strained Ge pMOS, the OFF-current target may be set at high T instead of RT, achieving further Ieff improvement over Si. These results illustrate the potential benefits of strain in Ge n-and pMOS and emphasize the importance of considering the operating T to correctly project the performance improvement.