PPU: Design and Implementation of a Pipelined Full Posit Processing Unit
arxiv(2023)
摘要
By exploiting the modular RISC-V ISA this paper presents the customization of
instruction set with posit™ arithmetic
instructions to provide improved numerical accuracy, well-defined behavior and
increased range of representable numbers while keeping the flexibility and
benefits of open-source ISA, like no licensing and royalty fee and community
development. In this work we present the design, implementation and integration
into the low-power Ibex RISC-V core of a full posit processing unit capable to
directly implement in hardware the four arithmetic operations (add, sub, mul,
div and fma), the inversion, the float-to-posit and posit-to-float conversions.
We evaluate speed, power and area of this unit (that we have called Full Posit
Processing Unit). The FPPU has been prototyped on Alveo and Kintex FPGAs, and
its impact on the metrics of the full-RISC-V core have been evaluated, showing
that we can provide real number processing capabilities to the mentioned core
with an increase in area limited to 7% for 8-bit posits and to 15% for
16-bit posits. Finally we present tests one the use of posits for deep neural
networks with different network models and datasets, showing minimal drop in
accuracy when using 16-bit posits instead of 32-bit IEEE floats.
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