A 128-GS/s Timing-Robust Sampling Architecture Exploiting Analog FFT.

Timing errors are the fundamental limitations of high-speed sampling systems. This paper proposes a high-speed sampling architecture with significantly improved timing-error robustness. During the analog calculation of the fast Fourier transform (FFT), the signal and noise behave differently with the superposition and correlation operations, resulting in improved sampling performance. In particular, the impact of timing skews, jitters and bandwidth mismatch is relaxed significantly. Exploiting a 64-channel radix-4 AFFT sampler, the proposed sampling system achieves 128GS/s with 7.93b effective number of bits (ENOB) at 30fs rms jitter. Compared with state-of-the-art time-interleaving systems, >10dB linearity enhancement has been observed with the same level of timing errors.