A Subthreshold-Inverter-Based Strong PUF with High Reliability and Energy Efficiency

ISCAS(2023)

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摘要
In this paper, we present an energy-efficient strong physical unclonable function (PUF) based on subthreshold inverters (STIs) that are regulated by a native NMOS transistor. Two groups of STIs can be dynamically regrouped to 4 stages according to the provided challenge, with each stage having different number of STIs connected in parallel. By adopting the first two stages as the entropy source and the last two stages for generating the PUF bits, the equivalent 4-stage STI chain can exhibit high reliability under largely varied temperature and supply voltage. Moreover, the proposed strong PUF implementation is validated using a standard 65-nm 1.2 V CMOS process. With the temperature and supply voltage changing from 0°C to 120°C and 0.7 V to 1.5 V, respectively, the worst-case bit error rate (BER) is reported to be 5.025%. Meanwhile, the energy consumption is simulated to be 0.26 pJ/bit at the maximum throughput of 10 Mb/s. Moreover, the proposed strong PUF shows high resilience to various machine learning (ML) attacks, including logistic regression, support vector machine and covariance matrix adaptation evolution strategy.
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关键词
4-stage STI chain,BER,covariance matrix adaptation evolution strategy,energy consumption,energy-efficient strong physical unclonable function,entropy source,high reliability,high resilience,largely varied temperature,logistic regression,machine learning attacks,ML attacks,native NMOS transistor,PUF bits,strong PUF implementation,subthreshold inverters,subthreshold-inverter-based strong PUF,supply voltage,support vector machine,temperature 0.0 degC to 120.0 degC,voltage 0.7 V to 1.5 V,worst-case bit error rate
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