A Multi-Pixel Compression for Low-Power Imaging System and Architecture.

Multi-pixel image sensors such as Tetra-Cell image sensor have been developed in recent years, and its pixel size is becoming smaller with high resolution. As the amount of pixel data being transmitted has increased, it consumes significantly higher power in the imaging system. Although many image compression algorithms have been studied to reduce the amount of pixel data, it comes with high-complexity, focuses on Bayer pattern, and even has challenges of geometrical distances on Tetra-Cell pattern. In this paper, we propose Multi-Pixel Compression (MPC) which can provide high image quality as well as high compression ratio on Tetra-Cell pattern. We also propose low-power imaging system with MPC. In the proposed imaging system, the power consumption of MIPI transmission and DRAM access can be reduced by 75%. The proposed MPC architecture is implemented as ASIC, its encoder design achieves energy efficiency 1.94 Gb/s/ mW and 1.29 Gb/s/mW on Bayer and Tetra-Cell pattern image, respectively, and it achieves 57.11dB PSNR, thus outperforming related previous work.