FPGA-Based Hardware-Accelerated Design of Linear Prediction Analysis for Real-Time Speech Signal

Linear prediction analysis is a crucial technique used in speech coding to compress speech signals and facilitate their reliable transmission over limited bandwidth or storage space. However, this technique involves repetitive computations on a wide range of incoming audio data, leading to high resource consumption and execution time. To address this challenge, an FPGA-based acceleration method is proposed in the present work that provides high computational capabilities and is energy efficient. The study focuses on optimizing linear prediction analysis at the sub-block level, specifically by modifying the autocorrelation and Levinson–Durbin algorithm to enhance the performance of the overall system. The suggested algorithm is integrated into a hardware/software co-design as a high-performance intellectual property with an AXI4-Stream interface. The system achieves over 99% speed increase and a 60% reduction in resource utilization, by the proposed hardware acceleration implementation. These findings are significant for designing optimized hardware for low bit rate speech coders with improved execution time and reduced resource consumption. The approach is validated by simulating and testing the complete system-on-chip architecture on a Zynq Zybo FPGA for functionality and real-time data performance.