3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.

Wordline driver sleep (WLSLP) and write driver sleep (WDSLP) circuits are introduced to reduce leakage power while keeping fast write speed. With WLSLP and WDSLP, leakage power is reduced by 71%. In our SRAM design, it demonstrates 3.7GHz at 1.4 V and wide-range operation down to 0.5 V. It achieves the best FoM defined as density × frequency.