E-Core Implementation in Intel 4 with PowerVia (backside Power) Technology.
M. Shamanna, E. Abuayob, G. Aenuganti, C. Alvares, J. Antony, A. Bahudhanam, A. Chandran, P. Chew,A. Chatterjee, B. Chauhan, N. Dandeti, J. Desai, M. Doyle, T. Dmukauskas, P. Farache, E. Fetzer, K. Fischer, P. Hack,Y. Greenzweig, J. Giacobbe,Walid M. Hafez, E. Haralson, A. Hegde, A. Illa, M. Islam,S. Jain,M. Jang, J. Nguyen, T. Tong, L. Jiang,Eric Karl, P. Kalangi, G. Khoo, A. Krishnamoorthy, B. Kuns, W. Li,R. Livengood, T. Malik, R. Priyanka, H. Faraby, Y. Maymon,K. Mistry, K. Morgan,S. Natarajan, O. Nevo,M. Oh, P. Pardy, J. Park, P. Penmatsa, B. Phelps, C. Peterson, S. Rajappa, A. Raveh, A Rezaie, T. Ravishankar,R. Ramaswamy, S. Reddy, R. Saha, S. Sen, R. Sanchez, R. Sanaga, B. Simkhovich,Bernhard Sell,M. Senger, B. Schnarch, M. Seshadri, O. Sidorov,S. Subramanian, K. Subramanian,B. Truong, S. Bangalore,Jeffery Hicks, S. Venkatesh, D. Christensen, K. Bhargav,M. Von Haartman, P. Joshi, S. Zickel, C.-H. Lin, J. Huening, T.-H. Wu, N. Bakken,A. Afzal, A. Raman, Sj. Rao, V. Kawar,J. Neirynck, D. Bradley, M. Duwe, S. Wu, V. Patil, M. Bayoumy 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2023）
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CMOS Scaling,Strained-Silicon Technology
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