E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology.

M. Shamanna, E. Abuayob, G. Aenuganti, C. Alvares, J. Antony, A. Bahudhanam, A. Chandran, P. Chew, A. Chatterjee, B. Chauhan, N. Dandeti, J. Desai, M. Doyle, T. Dmukauskas, P. Farache, E. Fetzer, K. Fischer, P. Hack, Y. Greenzweig, J. Giacobbe,Walid M. Hafez, E. Haralson, A. Hegde, A. Illa, M. Islam, S. Jain,M. Jang, J. Nguyen, T. Tong, L. Jiang,Eric Karl, P. Kalangi, G. Khoo, A. Krishnamoorthy, B. Kuns, W. Li,R. Livengood, T. Malik, R. Priyanka, H. Faraby, Y. Maymon,K. Mistry, K. Morgan, S. Natarajan, O. Nevo,M. Oh, P. Pardy, J. Park, P. Penmatsa, B. Phelps, C. Peterson, S. Rajappa, A. Raveh, A Rezaie, T. Ravishankar,R. Ramaswamy, S. Reddy, R. Saha, S. Sen, R. Sanchez, R. Sanaga, B. Simkhovich,Bernhard Sell,M. Senger, B. Schnarch, M. Seshadri, O. Sidorov, S. Subramanian, K. Subramanian,B. Truong, S. Bangalore, Jeffery Hicks, S. Venkatesh, D. Christensen, K. Bhargav,M. Von Haartman, P. Joshi, S. Zickel, C.-H. Lin, J. Huening, T.-H. Wu, N. Bakken,A. Afzal, A. Raman, Sj. Rao, V. Kawar,J. Neirynck, D. Bradley, M. Duwe, S. Wu, V. Patil, M. Bayoumy

Symposium on VLSI Circuits（2023）

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Abstract

PowerVia Technology [1] is a novel innovation to extend Moore’s Law scaling by having Power Delivery on the backside. This paper presents the pre & post-silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of >90% in large areas of the core while showing >5% Frequency benefit in Silicon due to reduced IR drop. Successful Post-Silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristic of the PowerVia test-chip is in line with higher power densities expected from logic scaling.

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