A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.

A 3-nm single-port (SP) 6T SRAM macro has been proposed using far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuit can reduce write cycle time to boost the pre-charge time and read cycle time to improve the trackability of supply voltage. We designed and fabricated a 434kbit SP SRAM macro on 3-nm FinFET technology. The bit density is $27.6-\mathrm{Mbit} / \mathrm{mm}^{2}$ and achieved 1.9GHz operation at $0.75 \mathrm{~V}$ which is 35% faster than conventional performance.