Efficient ASIC Implementation for Satellite-IoT Security Co-processor.

ASIC implementation of a security co-processor for Satellite-IoT devices is introduced. It provides a hardware acceleration for AES-GCM, the CCSDS-compliant Authenticated Encryption algorithm. The Key size is programmable, supporting both 128 and 256-bit modes, to comply with baseline implementation of CCSDS SDLS protocol, and Extended Procedures. Implementation targets 65nm CMOS technology using low-power standard cell library, resulting in a synthesis cell area of 52.2kGE. Achieving max. clock frequency of 617.3MHz, data throughput is 7.18Gbps for 128-bit mode, and 5.27Gbps for 256-bit mode. Output Tag throughput is 418 and 333Mbps, for 128-bit and 256bit modes, respectively. Implementation is primarily optimized for power to cater for battery-operated IoT devices. Average post-synthesis energy consumption is 1.25pJ/bit at 128-bit mode, which is almost the same as the most efficient design in literature with >91% area saving. Energy consumption is 1.54pJ/bit for the 256-bit mode. Post-PnR’s GDSII area is 125.2µm ² , and energy consumption is 2.82 and 3.55pJ/bit, for 128 and 256-bit modes, respectively.