A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.

Jonathan Chang,Yen-Huei Chen,Gary Chan, Kuo-Cheng Lin,Po-Sheng Wang,Yangsyu Lin,Sevic Chen, Peijiun Lin,Ching-Wei Wu,Chih-Yu Lin,Yi-Hsin Nien,Hidehiro Fujiwara,Atul Katoch,Robin Lee,Hung-Jen Liao,Jhon-Jhy Liaw,Shien-Yang Michael Wu,Quincy Li

VLSI Technology and Circuits（2023）

Cited 0|Views21

No score

Abstract

This paper presents a 3nm 256Mb SRAM in FinFET technology with interleaved triple WL scheme and new array banking architecture for low V MIN applications.

Translated text

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined