A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.

In this work, we present a continuous-time (CT) pipeline ADC with time-interleaved sub-ADC-DAC path in its first stage. The proposed sub-ADC-DAC path helps in increasing the ADC bandwidth by improving the signal cancellation at the stage-1 summing node. We have also designed an inductorless delay line for the first stage to improve amplitude and phase matching which reduces the input signal leakage into the backend ADC. A prototype ADC was fabricated in 16nm FinFET process. The ADC achieves 61.7/60.8dB (low/high frequency) SNR over 1-GHz bandwidth. The active area is 0.77m$\mathrm{m}^{2}$ and the ADC consumes 240mW. The Schreier figure-of-merit ($\mathrm{FOM}_{\mathrm{S}}$) is 157.9dB which is amongst the best for ADCs with digitization bandwidth greater than 500MHz.