A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology.
VLSI Technology and Circuits(2023)
Abstract
A high speed IRIW two port 32Kbit (128×256) SRAM with single port 6T bitcell macro is proposed. A Read-Then-Write (RTW) double pump CLK generation circuit with TRKBL bypassing is proposed to enhance read performance. Double metal scheme is applied to improve signal integrity and overall operating cycle time. A Local Interlock Circuit (LIC) is introduced in Sense-Amp to reduce active power and push Fmax further. The silicon results show that the slow corner wafer was able to achieve 4. 24GHz at 1.0V/100°C in 5nm FinFET technology.
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Key words
1R1W,SRAM,double pump,5nm
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