Nanosheet-based Complementary Field-Effect Transistors (cfets) at 48nm Gate Pitch, and Middle Dielectric Isolation to Enable CFET Inner Spacer Formation and Multi-Vt Patterning.
Hans Mertens,M. Hosseini,Thomas Chiarella,D. Zhou,S. Wang,G. Mannaert,E. Dupuy,D. Radisic,Z. Tao,Y. Oniki,Andriy Hikavyy, R. Rosseel, A. Mingardi,S. Choudhury,P. Puttarame Gowda,F. Sebaai,A. Peter,Kevin Vandersmissen,J. P. Soulie,An De Keersgieter,L. Petersen Barbosa Lima, C. Cavalcante,D. Batuk,G. T. Martinez,J. Geypen,F. Seidel, K. Paulussen,P. Favia,Jürgen Bömmels,Roger Loo,P. Wong, A. Sepulveda Marquez,B. T. Chan,Jérôme Mitard,S. Subramanian,S. Demuynck,E. Dentoni Litta,N. Horiguchi,S. Samavedam,S. Biesemans 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2023）
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