A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR.

VLSI Technology and Circuits(2023)

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摘要
This paper presents a level crossing ADC (LC-ADC) for biomedical applications. The ADC uses dynamically biased comparators, which require minimal power when the input voltage is far away from a decision threshold. This results in >10x better power efficiency compared to prior LC-ADCs when converting sparse signals. In a 16 kHz bandwidth, the LC-ADC achieves a 61.4 dB SNDR resulting in an efficiency of 3 fJ/conv.step for sparse input signals.
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61.4 dB SNDR,61.4 dB-SNDR,biomedical applications,continuous time level crossing ADC,dynamic self-biasing comparators,energy 320.0 fJ,frequency 16.0 kHz,input voltage,LC-ADC,minimal power,noise figure 61.4 dB,power efficiency,sparse input signals
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