A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application.

In this paper, we present the design of a new low-power, high-performance MOS Current Mode Logic (MCML) D-Latch. The proposed design consists of cross-coupled transistors which dynamically control the load resistance and eliminate static power dissipation. The performance of the design was improved by reducing the threshold voltage of the input transistors at the critical phase to switch them ON faster using the clocked-driven forward body biasing technique. The proposed design achieves an energy improvement of 54% and 49% and a performance improvement of 20% and 43% compared to the Folded and Folded (DTMOS) D-Latches, respectively. The designs were simulated on Cadence Virtuoso ADE tool using 40 nm technology TSMC PDK. Moreover, the proposed design provides higher output voltage swing and is less sensitive to the change of load capacitance compared to the other designs.