A High Efficiency Hardware Accelerator for Convolution Neural Network

A convolutional neural network accelerator that can efficiently process AlexNet’s convolutional neural network architecture is developed. The processing element (PE) array can perform operations on each layer of convolution by simply setting the input feature map (ifmap) size, filter size, and other convolutional model settings before inputting data. The PE array then selects the optimal segmentation method based on these settings for each operation. The calculation values are transmitted through a data bus from the global buffer, which stores input feature maps, filters, and other relevant data. The partial sums obtained by the PE operation are also transmitted back to the global buffer through the data bus. After the complete operation, the output feature map is passed through the ReLU function and data compression encoder before being transmitted back to the off-chip memory through another data bus. Both numbers and times of ifmap passed will be greater than those of filters. To accommodate the high throughput of ifmap, the width of the scratch pad (spad) and buses for ifmap are designed to be larger.