A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC

Pseudo-Pseudo-Differential (PPD) architecture can achieve higher power-efficiency with greatly reduced hardware complexity compared with fully- or pseudo-differential architectures. This paper analyzes the operation of PPD delta-sigma ADC, identifying a delay mismatch between the differential loops, which needs special treatment for stability. Resonator and common-mode feedback implementation is explored. Based on the analysis, a 3 ^rd -order PPD delta-sigma ADC is designed for 16-bit accuracy with 100kHz bandwidth at 9.6MS/s sampling speed.