A New ATPG and Online Monitoring based Technique for Hardware Trojan Detection

Hardware Trojan (HT) is the most severe security threat during an integrated circuit (IC) development. The logic testing based pre-silicon techniques fail to detect the HT inserted during fabrication, whereas the existing ATPG based approaches provide low coverage and are inefficient to trigger hard-to-activate sites. Further, the existing online monitoring techniques fail to detect the Trojans effectively and do not provide any opportunity to fix/reject the design. Therefore, a new HT detection technique is proposed that combines ATPG and online monitoring to detect all the stealthy Trojans effectively. This paper first proposes a new ATPG algorithm that generates the patterns to activate the Trojan. Further, a new modified HT detection (checker) logic is proposed that is selectively inserted in the original design to effectively observe the effect of activated Trojan during post-silicon testing and online monitoring. The proposed checker logic eliminates the masking problem and can also observe the effects of those HTs, which could not propagate to the output. The experimental evaluation on ISCAS benchmarks shows that our algorithm provides 4.5x higher trigger coverage and does not leave any feasible rare-node inactivated. Further, the proposed checker effectively observes malicious behavior without additional overhead over the existing checker. The insertion of our checker at 25% low observability nodes in ISCAS benchmarks requires only 0.189% area overhead.