Engineering negative differential resistance in negative capacitance Quad-FinFET

•We systematically investigated the impact of ferroelectric (FE) layer thickness (tFE) on the electrical parameters of a Negative Capacitance QuadFinFET (NC-QuadFinFET) using 3D TCAD simulator.•The Increase in tFE leads to higher ION/IOFF current ratio but also enhances hysteresis. However, it is also witnessed that at a certain ferroelectric layer thickness, the NC-QuadFinFET suffers from negative DIBL owing to Negative Differential Resistance (NDR).•Although NDR is beneficial for oscillator designs, it is undesirable for most analog circuits. Hence, keeping the same gate length and tFE fixed, the NC-quadFinFET is further optimized using alternative techniques to reduce the NDR effects.•By extending the drain length and with the implementation of Si3N4 Spacer, an enhancement in the electrical parameters as well as the intrinsic gain of the device is exhibited.•The NC Quad-FinFET with drain engineered and Si3N4 spacer implementation as a digital inverter shows a considerable 27.65% decrement in the circuit propagation delay. As a result, the optimized NC-quadFinFET is a potential candidate for ultralow-power applications and analog circuits.