Influence of channel length and layout on TID for 0.18 μm NMOS transistors

Different channel lengths and layouts on 0.18 μm NMOS transistors are designed for investigating the dependence of short channel effects (SCEs) on the width of shallow trench isolation (STI) devices and designing in radiation hardness. Results show that, prior to irradiation, the devices exhibited near–ideal I–V characteristics, with no significant SCEs. Following irradiation, no noticeable shift of threshold voltage is observed, radiation–induced edge–leakage current, however, exhibits significant sensitivity on TID. Moreover, radiation–enhanced drain induced barrier lowering (DIBL) and channel length modulation (CLM) effects are observed on short–channel NMOS transistors. Comparing to stripe–gate layout, enclosed–gate layout has excellent radiation tolerance.